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Preliminary Technical Data
FEATURES
Precision, Dual-Channel, JFET Input Rail-to-Rail Instrumentation Amplifier AD8224
FUNCTIONAL BLOCK DIAGRAM
OUT1 OUT2
14
Two channels in a small 4 mm x 4 mm LFCSP Low input currents 10 pA maximum input bias current (B grade) 0.6 pA maximum input offset current (B grade) High CMRR 100 dB CMRR (minimum), G = 10 (B grade) 80 dB CMRR (minimum) to 5 kHz, G = 1 (B grade) Excellent ac specifications and low power 1.5 MHz bandwidth (G = 1)
14 nV/Hz input noise (1 kHz)
Slew rate 2 V/s
750 A quiescent supply current per amplifier (maximum)
Versatility Rail-to-rail output Input voltage range to below negative supply rail 4 kV ESD protection 4.5 V to 36 V single supply 2.25 V to 18 V dual supply Gain set with single resistor (G = 1 to 1000)
+VS
16
15
-IN1 RG1 RG1 +IN1
AD8224
1 2 3 4 12 11 10 9
-VS
13
-IN2 RG2 RG2 +IN2
5
6
7
8
06286-001
REF1
REF2
+VS
Figure 1. 4mm x 4 mm LFCSP
Table 1. In Amps and Difference Amplifiers by Category
High Perform. AD82201 AD8221 AD8222 AD82241
1
Low Cost AD85531 AD6231
High Volt. AD628 AD629
APPLICATIONS
Medical instrumentation Precision data acquisition Transducer interface Differential drive for High resolution input ADCs Remote sensors
Mil Grade AD620 AD621 AD524 AD526 AD624
-VS
Low Power AD6271
Digital Gain AD85551 AD85561 AD85571
Rail-to-rail output.
GENERAL DESCRIPTION
The AD8224 is the first single-supply junction field effect transistor (JFET) input instrumentation amplifier available in the space-saving 16-lead, 4 mmx4 mm LFCSP. It requires the same board area as a typical single instrumentation amplifier, yet doubles the channel density and offers a lower cost per channel without compromising performance. Designed to meet the needs of high performance, portable instrumentation, the AD8224 has a minimum common-mode rejection ratio (CMRR) of 86 dB at dc and a minimum CMRR of 80 dB at 5 kHz for G = 1. Maximum input bias current is 10 pA and typically remains below 300 pA over the entire industrial temperature range. Despite the JFET inputs, the AD8224 typically has a noise corner of only 10 Hz. With the proliferation of mixed-signal processing, the number of power supplies required in each system has grown.
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by AnalogDevices for its use,nor for any infringements of patents or other rightsof third parties that mayresult from its use. Specifications subject to change withoutnotice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registeredtrademarks arethe property oftheir respective owners.
Designed to alleviate this problem, the AD8224 can operate on a 18 V dual supply, as well as on a single +5 V supply. The device's rail-to-rail output stage maximizes dynamic range on the low voltage supplies common in portable applications. Its ability to run on a single 5 V supply eliminates the need for higher voltage, dual supplies. The AD8224 draws a maximum of 750 A of quiescent current per amplifier, making it ideal for battery-powered devices. In addition, the AD8224 can be configured as a single-channel, differential output instrumentation amplifier. Differential outputs provide high noise immunity, which can be useful when the output signal must travel through a noisy environment, such as with remote sensors. The configuration can also be used to drive differential input ADCs. For a single-channel version, use the AD8220 device.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
AD8224 TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History .......................... Error! Bookmark not defined.
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 20
Gain Selection ............................................................................. 20
Reference Terminal .................................................................... 21
Preliminary Technical Data
Layout .......................................................................................... 21
Solder Wash................................................................................. 22
Input Bias Current Return Path ............................................... 22
Input Protection ......................................................................... 22
RF Interference ........................................................................... 22
Common-Mode Input Voltage Range ..................................... 23
Applications..................................................................................... 24
Driving an Analog-to-Digital Converter ................................ 24
Differential Output .................................................................... 24
Driving a Differential Input ADC............................................ 25
Driving Cabling .......................................................................... 25
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 26
Rev. PrB | Page 2 of 27
Preliminary Technical Data SPECIFICATIONS
VS+ = +15 V, VS- = -15 V, VREF = 0 V, TA = +25C, G = 1, RL = 2 k, unless otherwise noted. Table 2. Single-Ended and Differential1 Output Configuration
A Grade Parameter COMMON-MODE REJECTION RATIO (CMRR) CMRR DC to 60 Hz with 1 k Source Imbalance G=1 G = 10 G = 100 G = 1000 CMRR at 5 kHz G=1 G = 10 G = 100 G = 1000 NOISE Voltage Noise, 1 kHz Input Voltage Noise, eni Output Voltage Noise, eno RTI, 0.1 Hz to 10 Hz G=1 G = 1000 Current Noise VOLTAGE OFFSET Input Offset, VOSI Average TC Output Offset, VOSO Average TC Offset RTI vs. Supply (PSR) G=1 G = 10 G = 100 G = 1000 INPUT CURRENT (PER CHANNEL) Input Bias Current Over Temperature2 Input Offset Current Over Temperature2 GAIN Gain Range Gain Error G=1 G = 10 G = 100 G = 1000 Gain Nonlinearity G=1 G = 10 G = 100 VOUT = -10 V to +10 V RL = 10 k RL = 10 k RL = 10 k
Rev. PrB | Page 3 of 27
AD8224
Test Conditions VCM = 10 V
Min
Typ
Max
Unit
78 94 94 94 VCM = 10 V 74 84 84 84 RTI noise = (eni2 + (eno/G)2) VIN+, VIN- = 0 V VIN+, VIN- = 0 V 14 90 5 0.8 f = 1 kHz RTI VOS = (VOSI) + (VOSO/G) 250 T = -40C to +85C T = -40C to +85C 86 96 96 96 25 T = -40C to +85C T = -40C to +85C G = 1 + (49.4 k/RG) 1 VOUT = 10 V 0.06 0.3 0.3 0.3 10 5 30 15 10 60 300 2 5 1000 10 750 10 1
dB dB dB dB dB dB dB dB
nVHz nVHz V p-p V p-p fA/Hz V V/C V V/C dB dB dB dB pA pA pA pA V/V % % % % ppm ppm ppm
AD8224
Parameter G = 1000 G=1 G = 10 G = 100 Gain vs. Temperature G=1 G > 10 INPUT Impedance (Pin to Ground)3 Input Operating Voltage Range Over Temperature OUTPUT Output Swing Over Temperature Output Swing Over Temperature Short-Circuit Current REFERENCE INPUT RIN IIN Voltage Range Gain to Output POWER SUPPLY (PER AMPLIFIER) Operating Range Quiescent Current Over Temperature TEMPERATURE RANGE For Specified Performance Operational6
1 2 3
Preliminary Technical Data
A Grade Test Conditions RL = 10 k RL = 2 k RL = 2 k RL = 2 k Min Typ 400 10 10 50 3 Max 500 15 15 75 10 -50 104||5
4
Unit ppm ppm ppm ppm ppm/C ppm/C G||pF
VS = 2.25 V to 18 V for dual supplies T = -40C to +85C RL = 2 k T = -40C to +85C RL = 10 k T = -40C to +85C
-VS - 0.1 -VS - 0.1 -14.3 -14.3 -14.7 -14.6 15 40
+VS - 2 +VS - 2.1 +14.3 +14.1 +14.7 +14.6
V V V V V V mA k
VIN+, VIN- = 0 V -VS 1 0.0001 2.255 T = -40C to +85C -40 -40
70 +VS
A V V/V
18 750 850 +85 +125
V A A C C
Refers to differential configuration shown in Figure 64.
Please refer to Figure 16 and Figure 17 for the relationship between input current and temperature.
Differential and common-mode input impedance can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2.
4 The AD8224 can operate up to a diode drop below the negative supply but the bias current increases sharply. The input voltage range reflects the maximum
allowable voltage where the input bias current is within the specification. 5 At this supply voltage, ensure that the input common-mode voltage is within the input voltage range specification. 6 The AD8224 is characterized from -40C to +125C. See the Typical Performance Characteristics section for expected operation in this temperature range.
Rev. PrB | Page 4 of 27
Preliminary Technical Data
VS+ = +15 V, VS- = -15 V, VREF = 0 V, TA = +25C, G = 1, RL = 2 k, unless otherwise noted. Table 3. Single-Ended Output Configuration--Dynamic Performance (Both Amplifiers)
Parameter DYNAMIC RESPONSE Small Signal Bandwidth -3 dB G=1 G = 10 G = 100 G =1000 Settling Time 0.01% G=1 G = 10 G = 100 G =1000 Settling Time 0.001% G=1 G = 10 G = 100 G =1000 Slew Rate G = 1 to 100 Conditions Min A Grade Typ Max
AD8224
Unit
TBD TBD TBD TBD 10 V step TBD TBD TBD TBD 10 V step TBD TBD TBD TBD TBD
kHz kHz kHz kHz s s s s s s s s V/s
Please fill in TBDs if you can.
VS+ = +15 V, VS- = -15 V, VREF = 0 V, TA = +25C, G = 1, RL = 2 k, unless otherwise noted.
Table 4. Differential Output Configuration1--Dynamic Performance
Parameter DYNAMIC RESPONSE Small Signal Bandwidth-3 dB G=1 G = 10 G = 100 G =1000 Settling Time 0.01% G=1 G = 10 G = 100 G =1000 Settling Time 0.001% G=1 G = 10 G = 100 G =1000 Slew Rate G = 1 to 100
1
Conditions
Min
A Grade Typ
Max
Unit
TBD TBD TBD TBD 10 V step TBD TBD TBD TBD 10 V step TBD TBD TBD TBD TBD
kHz kHz kHz kHz s s s s s s s s V/s
Refers to differential configuration shown in Figure 64.
Rev. PrB | Page 5 of 27
AD8224
VS + = 5 V, VS- = 0 V, VREF = 2.5 V, TA = +25C, G = 1, RL = 2 k, unless otherwise noted. Table 5. Single-Ended and Differential1 Output Configuration
Parameter COMMON-MODE REJECTION RATIO (CMRR) CMRR DC to 60 Hz with 1 k Source Imbalance G=1 G = 10 G = 100 G = 1000 CMRR at 5 kHz G=1 G = 10 G = 100 G = 1000 NOISE Voltage Noise, 1 kHz Input Voltage Noise, eni Output Voltage Noise, eno RTI, 0.1 Hz to 10 Hz G=1 G = 1000 Current Noise VOLTAGE OFFSET Input Offset, VOSI Average TC Output Offset, VOSO Average TC Offset RTI vs. Supply (PSR) G=1 G = 10 G = 100 G = 1000 INPUT CURRENT (PER CHANNEL) Input Bias Current Over Temperature2 Input Offset Current Over Temperature2 GAIN Gain Range Gain Error G=1 G = 10 G = 100 G = 1000 Nonlinearity G=1 G = 10 G = 100
VCM = 0 to 2.5 V
Preliminary Technical Data
Test Conditions
Min
A Grade Typ
Max
Unit
78 94 94 94 74 84 84 84 RTI noise = (eni2 + (eno/G)2) VIN+, VIN- = 0 V, VREF = 0 V VIN+, VIN- = 0 V, VREF = 0 V 14 90 5 0.8 1 300 10 800 10 86 96 96 96 25 T = -40C to +85C T = -40C to +85C G = 1 + (49.4 k/RG) 1
VOUT = 0.3 V to 2.9 V for G = 1 VOUT = 0.3 V to 3.8 V for G > 1
dB dB dB dB dB dB dB dB
nVHz nVHz V p-p V p-p fA/Hz V V/C V V/C dB dB dB dB pA pA pA pA V/V
f = 1 kHz
RTI VOS = (VOSI) + (VOSO/G)
T = -40C to +85C T = -40C to +85C
300 2 5 1000
0.06 0.3 0.3 0.3
VOUT = 0.3 V to 2.9 V for G = 1 VOUT = 0.3 V to 3.8 V for G > 1
% % % %
RL = 10 k RL = 10 k RL = 10 k
Rev. PrB | Page 6 of 27
35 35 50
50 50 75
ppm ppm ppm
Preliminary Technical Data
Parameter G = 1000 G=1 G = 10 G = 100 Gain vs. Temperature G=1 G > 10 INPUT Impedance (Pin to Ground)3 Input Voltage Range Over Temperature OUTPUT Output Swing Over Temperature Output Swing Over Temperature Short-Circuit Current REFERENCE INPUT RIN IIN Voltage Range Gain to Output POWER SUPPLY (PER AMPLIFIER) Operating Range Quiescent Current Over Temperature TEMPERATURE RANGE For Specified Performance Operational5
1 2
AD8224
Test Conditions RL = 10 k RL = 2 k RL = 2 k RL = 2 k Min A Grade Typ 650 35 35 50 3 Max 750 50 50 75 10 -50 Unit ppm ppm ppm ppm ppm/C ppm/C G||pF +VS - 2 V +VS - 2. V 4.75 4.70 4.85 4.80 15 40 VIN+, VIN- = 0 V -VS 1 0.0001 +4.5 T = -40C to +85C -40 -40 +36 750 850 +85 +125 70 +VS V V V V mA k A V V/V V A A C C
104||6 T = -40C to +85C RL = 2 k T = -40C to +85C RL = 10 k T = -40C to +85C -0.1 -0.1 0.25 0.3 0.15 0.2
4
Refers to differential configuration shown in Figure 64.
Refer to Figure 16 and Figure 17 for the relationship between input current and temperature.
3 Differential and common-mode impedance can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2.
4 The AD8224 can operate up to a diode drop below the negative supply but the bias current increases sharply. The input voltage range reflects the maximum
allowable voltage where the input bias current is within the specification. 5 The AD8224 is characterized from -40C to +125C. See the Typical Performance Characteristics section for expected operation in that temperature range.
Rev. PrB | Page 7 of 27
AD8224
VS + = 5 V, VS- = 0 V, VREF = 2.5 V, TA = +25C, G = 1, RL = 2 k, unless otherwise noted. Table 6. Single-Ended Output Configuration--Dynamic Performance (Both Amplifiers)
Parameter DYNAMIC RESPONSE Small Signal Bandwidth -3 dB G=1 G = 10 G = 100 G =1000 Settling Time 0.01% G=1 G = 10 G = 100 G =1000 Settling Time 0.001% G=1 G = 10 G = 100 G =1000 Slew Rate G = 1 to 100 Conditions
Preliminary Technical Data
Min
A Grade Typ
Max
TBD TBD TBD TBD 3 V Step 4 V Step 4 V Step 4 V Step 3 V Step 4 V Step 4 V Step 4 V Step TBD TBD TBD TBD TBD TBD TBD TBD TBD
VS + = 5 V, VS- = 0 V, VREF = 2.5 V, TA = +25C, G = 1, RL = 2 k, unless otherwise noted. Table 7. Differential Output Configuration1--Dynamic Performance
Parameter DYNAMIC RESPONSE Small Signal Bandwidth -3 dB G=1 G = 10 G = 100 G =1000 Settling Time 0.01% G=1 G = 10 G = 100 G =1000 Settling Time 0.001% G=1 G = 10 G = 100 G =1000 Slew Rate G = 1 to 100
1
Conditions
Min
A Grade Typ
Max
Unit
TBD TBD TBD TBD 3 V Step 4 V Step 4 V Step 4 V Step 3 V Step 4 V Step 4 V Step 4 V Step TBD TBD TBD TBD TBD TBD TBD TBD TBD
kHz kHz kHz kHz s s s s s s s s V/s
Refers to differential configuration shown in Figure 64.
Rev. PrB | Page 8 of 27
Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS
Table 8.
Parameter Supply Voltage Power Dissipation Output Short Circuit Current Input Voltage (Common Mode) Differential Input Voltage Storage Temperature Operating Temperature Range2 Lead Temperature Range (Soldering 10 sec) Junction Temperature Package Glass Transition Temperature ESD (Human Body Model) ESD (Charge Device Model) ESD (Machine Model)
1 2
AD8224
Maximum Power Dissipation
Rating 18 V See Figure 2 Indefinite1 Vs Vs -65C to +130C -40C to +125C 300C 130C 130C 4 kV 1 kV 0.4 kV
The maximum safe power dissipation for the AD8224 is limited by the associated rise in junction temperature (TJ) on the die. At approximately 130C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the amplifiers. Exceeding a temperature of 130C for an extended period can result in a loss of functionality. Figure 2 shows the maximum safe power dissipation in the package vs. the ambient temperature for the LFCSP on a 4-layer JEDEC standard board.
4.0 3.5 3.0 JA = 48C/W WHEN THERMAL PAD IS SOLDERED TO BOARD
MAX POWER (W)
Assumes the load is referenced to mid-supply. Temperature for specified performance is -40C to +85C. For performance to +125C, see the Typical Performance Characteristics section.
2.5 2.0 1.5 1.0 0.5 JA = 86C/W WHEN THERMAL PAD IS NOT SOLDERED TO BOARD
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability.
THERMAL RESISTANCE
Table 9.
Thermal Pad Soldered to Board Not Soldered to Board JA 48 86 Unit C/W C/W
AMBIENT TEMPERATURE (C)
Figure 2. Maximum Power Dissipation
ESD CAUTION
The JA values in Table 9 assume a 4-layer JEDEC standard board. If the thermal pad is soldered to the board, then it is also assumed it is connected to a plane. JC at the exposed pad is 4.4C/W.
Rev. PrB | Page 9 of 27
06286-002
0 -60
-40
-20
0
20
40
60
80
100
120
140
AD8224 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
15 OUT1 14 OUT2 13 -VS 16 +VS
Preliminary Technical Data
-IN1 1 RG1 2 RG1 3 +IN1 4
PIN 1 INDICATOR
12 -IN2 11 RG2 10 RG2 9 +IN2
06286-003
AD8224
TOP VIEW
+VS 5
Figure 3. Pin Configuration
Table 10. Pin Function Descriptions
Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic -IN1 RG1 RG1 +IN1 +VS REF1 REF2 -VS +IN2 RG2 RG2 -IN2 -VS OUT2 OUT1 +VS Description Negative Input In-Amp 1. Gain Resistor In-Amp 1. Gain Resistor In-Amp 1. Positive Input In-Amp 1. Positive Supply. Reference Adjust In-Amp 1. Reference Adjust In-Amp 2. Negative Supply. Positive Input In-Amp 2. Gain Resistor In-Amp 2. Gain Resistor In-Amp 2. Negative Input In-Amp 2. Negative Supply. Output In-Amp 2. Output In-Amp 1. Positive Supply.
Rev. PrB | Page 10 of 27
REF1 6 REF2 7
-VS 8
Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS
AD8224
Figure 4. Typical Distribution of CMRR (G = 1)
Figure 7. Typical Distribution of Input Bias Current
Figure 5. Typical Distribution of Input Offset Voltage
1000
Figure 8. Typical Distribution of Input Offset Current
GAIN = +100 BANDWIDTH ROLL-OFF 100 GAIN = +1
(nV/ Hz)
GAIN = +10 10 GAIN = 100/GAIN = +1000
GAIN = +1000 BANDWIDTH ROLL-OFF
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 6. Typical Distribution of Output Offset Voltage
Figure 9. Voltage Spectral Density vs. Frequency
Rev. PrB | Page 11 of 27
06286-009
1
AD8224
XX 150 130 110
Preliminary Technical Data
GAIN = +1000 GAIN = +100 GAIN = +10 BANDWIDTH LIMITED
PSRR (dB)
XXX (X)
90 70 50 30
GAIN = +1
5V/DIV XX XX XXX (X)
1s/DIV
06286-010
XX
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 10. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1)
XX 150 130 110
Figure 13. Positive PSRR vs. Frequency, RTI
GAIN = +1000
PSRR (dB)
XXX (X)
90 GAIN = +1 70 GAIN = +10 50 GAIN = +100 30
1V/DIV XX XX XXX (X)
1s/DIV
06286-011
XX
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000)
8 7
INPUT BIAS CURRENT (pA)
9
Figure 14. Negative PSRR vs. Frequency, RTI
0.3 INPUT OFFSET CURRENT 15 INPUT OFFSET CURRENT 5 0.2 0.1 0 5 -15.1V -0.1 -0.2 -5.1V 1 INPUT BIAS CURRENT 5 INPUT BIAS CURRENT 15 -0.3 -0.4 -1 -16 -0.5
6 5 4 3 2 1 0 0.1
7
3
INPUT OFFSET CURRENT (pA)
06286-015
VOSI (V)
06286-012
1
10 TIME (s)
100
1k
-12
-8
-4
0
4
8
12
16
COMMON-MODE VOLTAGE (V)
Figure 12. Change in Input Offset Voltage vs. Warmup Time
Figure 15. Input Current vs. Common-Mode Voltage
Rev. PrB | Page 12 of 27
06286-014
10
06286-013
10
Preliminary Technical Data
160
10n
AD8224
140
GAIN = +1000
INPUT BIAS CURRENT (A)
1n 100p 10p 1p 0.1p
IBIAS
120
CMRR (dB)
100
GAIN = +100 GAIN = +1 BANDWIDTH LIMITED
IOS
80
GAIN = +10
60
-50
-25
0
25
50
75
100
125
150
1
10
100
1k
10k
100k
TEMPERATURE (C)
FREQUENCY (Hz)
Figure 16. Input Bias Current and Offset Current Temperature, VS = 15 V, VREF = 0 V
Figure 19. CMRR vs. Frequency, 1 k Source Imbalance
10
10n 1n
8 6
IBIAS
4 CMRR (V/V) 2 0 -2 -4 -6
CURRENT (A)
100p 10p 1p 0.1p IOS
-8 -30 -10 10 30 50 70 90 110 130
06286-020
-50
-25
0
25
50
75
100
125
150
TEMPERATURE (C)
06286-017
-10 -50
TEMPERATURE (C)
Figure 17. Input Bias Current and Offset Current vs. Temperature, VS = +5 V, VREF = 2.5 V
160 GAIN = +1000 70 60 140 50 40 30 GAIN = +10 100 GAIN = +1 80
Figure 20. Change in CMRR vs. Temperature, G = 1
GAIN = +1000
120 CMRR (dB)
GAIN = +100
GAIN = +100
GAIN (dB)
BANDWIDTH LIMITED
20 10 0 -10
GAIN = +10
GAIN = +1
60
-20 -30
06286-018
100
1k FREQUENCY (Hz)
10k
100k
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 18. CMRR vs. Frequency
Figure 21. Gain vs. Frequency
Rev. PrB | Page 13 of 27
06286-021
40 10
-40 100
06286-019
06286-016
40
AD8224
Preliminary Technical Data
NONLINEARITY (500ppm/DIV)
NONLINEARITY (5ppm/DIV)
RLOAD = 2k
XXX
XXX
RLOAD = 2k
RLOAD = 10k
RLOAD = 10k
06286-022
VS = 15V -10 -8 -6 -4 -2 0 VIN (V) 2 4 6 8 10
VS = 15V -10 -8 -6 -4 -2 0 2 4 6 8 10
OUTPUT VOLTAGE (V)
Figure 22. Gain Nonlinearity, G = 1
18
Figure 25. Gain Nonlinearity, G = 1000
INPUT COMMON-MODE VOLTAGE (V)
+13V 12 15V SUPPLIES
NONLINEARITY (5ppm/DIV)
RLOAD = 2k
6
-14.8V, +5.5V -4.8V, +0.6V
+3V
+14.9V, +5.5V +4.95V, +0.6V
XXX
0
5V SUPPLIES -4.8V, -3.3V +4.95V, -3.3V -5.3V +14.9V, -8.3V
RLOAD = 10k
-6
-14.8V, -8.3V
-12 -15.3V -12 -8 -4 0 4 8 12 16
06286-026 06286-027
VS = 15V -10 -8 -6 -4 -2 0 VIN (V) 2 4 6 8
06286-023
10
-18 -16
OUTPUT VOLTAGE (V)
Figure 23. Gain Nonlinearity, G = 10
Figure 26. Input Common-Mode Voltage Range vs. Output Voltage, G = 1, VREF = 0 V
4
INPUT COMMON-MODE VOLTAGE (V)
3
+3V
NONLINEARITY (50ppm/DIV)
RLOAD = 2k RLOAD = 10k
2 +0.1V, +1.7V 1 +4.9V, +1.7V +5V SINGLE SUPPLY, VREF = +2.5V +0.1V, +0.5V 0 -0.3V -1 -1 +4.9V, +0.5V
XXX
VS = 15V -10 -8 -6 -4 -2 0 2 4 6 8
06286-024
10
0
1
2
3
4
5
6
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Figure 24. Gain Nonlinearity, G = 100
Figure 27. Input Common-Mode Voltage Range vs. Output Voltage, G = 1, VS = +5 V, VREF = 2.5 V
Rev. PrB | Page 14 of 27
06286-025
Preliminary Technical Data
18
VS+
AD8224
-1 -2 -40C +85C
INPUT COMMON-MODE VOLTAGE (V)
+13V 12 15V SUPPLIES
+25C
6
OUTPUT SWING (V)
-3 -4
-14.9V, +5.4V -4.9V, +0.4V
+3V
+14.9V, +5.4V +4.9V, +0.5V
+125C
0
5V SUPPLIES -4.9V, -4.1V -6 -14.8V, -9V -12 -15.3V -18 -16 -5.3V +4.9V, -4.1V +14.9V, -9V
+4 +3 +2 +125C +1 VS - +85C +25C -40C
06286-028
-12
-8
-4
0
4
8
12
16
2
4
6
8
10
12
14
16
18
OUTPUT VOLTAGE (V)
DUAL SUPPLY VOLTAGE (V)
Figure 28. Input Common-Mode Voltage Range vs. Output Voltage, G = 100, VREF = 0 V
4
Figure 31. Output Voltage Swing vs. Supply Voltage, RL = 2 k, G = 10, VREF = 0 V
VS+ -0.2
INPUT COMMON-MODE VOLTAGE (V)
3
+3V
+125C
-0.4
+85C
+25C
-40C
2 +0.1V, +1.7V 1 +4.9V, +1.7V
+5V SINGLE SUPPLY, VREF = +2.5V
0 +0.1V, -0.5V -1 -1 -0.3V 2 3 +4.9V, -0.5V
OUTPUT SWING (V)
+0.4 +0.2
06286-029
+125C
+85C
+25C
-40C
0
1
4
5
6
2
4
6
8
10
12
14
16
18
OUTPUT VOLTAGE (V)
DUAL SUPPLY VOLTAGE (V)
Figure 29. Input Common-Mode Voltage Range vs. Output Voltage, G = 100, VS = +5 V, VREF = 2.5 V
VS+ -1 -2 +25C +85C NOTES 1. THE AD8224 CAN OPERATE UP TO A VBE BELOW THE NEGATIVE SUPPLY, BUT THE BIAS CURRENT WILL INCREASE SHARPLY. +1 -40C VS- -1 +25C +85C +125C
Figure 32. Output Voltage Swing vs. Supply Voltage, RL = 10 k, G = 10, VREF = 0 V
15
-40C
+125C
VOLTAGE SWING (V)
10
-40C +25C
INPUT VOLTAGE (V)
5 +125C 0
+85C
-5
+125C +85C
-10
+25C -40C
06286-033
2
4
6
8
10
12
14
16
18
06286-030
-15 100
1k RLOAD ()
10k
VOLTAGE SUPPLY (V)
Figure 30. Input Voltage Limit vs. Supply Voltage, G = 1, VREF =0 V
Figure 33. Output Voltage Swing vs. Load Resistance VS = 15 V, VREF = 0 V
Rev. PrB | Page 15 of 27
06286-032
VS -
06286-031
AD8224
5 -40C 4 +25C +125C 3 +85C XX NO LOAD
Preliminary Technical Data
47pF 100pF
VOLTAGE SWING (V)
2
1
+125C -40C
+25C
+85C 20mV/DIV XX XX 5s/DIV XX XXX (X)
06286-037 06286-039 06286-038
RLOAD ()
06286-034
0 100
1k
10k
Figure 34. Output Voltage Swing vs. Load Resistance VS = +5 V, VREF = 2.5 V
VS+ -1 -40C +125C +85C +25C
XXX (X)
Figure 37. Small Signal Pulse Response for Various Capacitive Loads, VS = 15 V, VREF = 0 V
XX 47pF NO LOAD 100pF
OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES
-2 -3 -4
+4 +3 +2 +1
06286-035
+125C
+85C
+25C
VS -
-40C 0 2 4 6 8 IOUT (mA) 10 12 14 16
XXX (X)
20mV/DIV XX XX
5s/DIV XX XXX (X)
Figure 35. Output Voltage Swing vs. Output Current, VS = 15 V, VREF = 0 V
VS+
Figure 38. Small Signal Pulse Response for Various Capacitive Loads, VS = +5 V, VREF = 2.5 V
35 30 25 20 15 10 5 0 100 GAIN = +10, +100, +1000 GAIN = +1
OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES
-1 +85C +125C -2
+25C
+2 +25C
+1
+125C
+85C
-40C VS -
06286-036
0
2
4
6
8 IOUT (mA)
10
12
14
16
OUTPUT VOLTAGE SWING (V p-p)
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 36. Output Voltage Swing vs. Output Current, VS = +5 V, VREF = 2.5 V
Figure 39. Output Voltage Swing vs. Large Signal Frequency Response
Rev. PrB | Page 16 of 27
Preliminary Technical Data
XX XX
AD8224
5V/DIV
5V/DIV
XXX (X)
0.002%/DIV
5s TO 0.01% 6s TO 0.001%
XXX (X)
0.002%/DIV
58s TO 0.01% 74s TO 0.001%
20s/DIV
06286-040
200s/DIV XX XX XXX (X)
06286-043
06286-045
XX XX XXX (X)
XX XX
Figure 40. Large Signal Pulse Response and Settle Time, G = 1, RL = 10 k, VS = 15 V, VREF = 0 V
XX
Figure 43. Large Signal Pulse Response and Settle Time, G = 1000, RL = 10 k, VS = 15 V, VREF = 0 V
5V/DIV
XXX (X)
0.002%/DIV
4.3s TO 0.01% 4.6s TO 0.001%
XXX
20mV/DIV
20s/DIV XX XXX (X)
06286-041
4s/DIV XXX
Figure 41. Large Signal Pulse Response and Settle Time, G = 10, RL = 10 k, VS = 15 V, VREF = 0 V
XX
Figure 44. Small Signal Pulse Response, G = 1, RL = 2 k, CL = 100 pF, VS = 15 V, VREF = 0 V
5V/DIV
XXX (X)
0.002%/DIV
8.1s TO 0.01% 9.6s TO 0.001%
XXX
20mV/DIV
20s/DIV XX XXX (X)
06286-042
XX XX
4s/DIV XXX
Figure 42. Large Signal Pulse Response and Settle Time, G = 100, RL = 10 k, VS = 15 V, VREF = 0 V
Figure 45. Small Signal Pulse Response, G = 10, RL = 2 k, CL = 100 pF, VS = 15 V, VREF = 0 V.
Rev. PrB | Page 17 of 27
06286-044
XX XX
AD8224
Preliminary Technical Data
XXX
20mV/DIV
XXX
20mV/DIV
06286-046
4s/DIV XXX
4s/DIV XXX
Figure 46. Small Signal Pulse Response, G = 100, RL = 2 k, C L= 100 pF, VS = 15 V, VREF =0 V
Figure 49. Small Signal Pulse Response, G = 10, RL = 2 k, CL = 100 pF,
VS = +5 V, VREF = 2.5 V
XXX
20mV/DIV
XXX
20mV/DIV
06286-047
40s/DIV XXX
4s/DIV XXX
Figure 47. Small Signal Pulse Response, G = 1000, RL = 2 k, CL = 100 pF, VS = 15 V, VREF = 0 V
Figure 50. Small Signal Pulse Response, G = 100, RL = 2 k, CL = 100 pF,
VS = +5 V, VREF = 2.5 V
XXX
20mV/DIV
XXX
20mV/DIV
06286-048
4s/DIV XXX
40s/DIV XXX
Figure 48. Small Signal Pulse Response, G = 1, RL = 2 k, CL = 100 pF, VS = +5 V, VREF = 2.5 V
Figure 51. Small Signal Pulse Response, G = 1000,RL = 2 k, CL = 100 pF,
VS = +5 V, VREF = 2.5 V
Rev. PrB | Page 18 of 27
06286-051
06286-050
06286-049
Preliminary Technical Data
15
AD8224
60 GAIN = +1000 40
SETTLING TIME (s)
10 SETTLED TO 0.001%
GAIN = +100
GAIN (dB)
20 GAIN = +10 0 GAIN = +1 -20
5
SETTLED TO 0.01%
06286-052
0
5
10
15
20
1k
10k
100k
1M
10M
OUTPUT VOLTAGE STEP SIZE (V)
FREQUENCY (Hz)
Figure 52. Settling Time vs. Step Size (G = 1) 15 V, VREF = 0 V
100
Figure 55. Differential Output Configuration: Gain vs. Frequency
100 90 80 CMROUT = 20 log
VDIFF_OUT VCM_OUT
SETTLING TIME (s)
70
CMROUT (dB)
SETTLED TO 0.001% 10 SETTLED TO 0.01%
60 50 40 30 20 10 1
LIMITED BY MEASUREMENT SYSTEM
10
100
1k
10k
100k
1M
GAIN (V/V)
FREQUENCY (Hz)
Figure 53. Settling Time vs. Gain for a 10 V Step, VS = 15 V, VREF = 0 V
Figure 56. Differential Output Configuration: Common-Mode Output vs. Frequency
Figure 54 Channel Separation vs. Frequency, RL = 2 k, Source Channel at G = 1
Rev. PrB | Page 19 of 27
06286-056
1
10
100
1000
06286-053
1
0
06286-055
0
-40 100
AD8224 THEORY OF OPERATION
+VS NODE A +VS RG +VS NODE B R2 24.7k +VS
Preliminary Technical Data
20k NODE F 20k A3 +VS OUTPUT 20k
R1 24.7k
-VS
-VS
+VS NODE C +IN J1 Q1 VPINCH C1 A1 A2 NODE D C2 Q2 J2
+VS NODE E -IN 20k +VS
-VS REF
-VS
VPINCH
-VS -VS
I
VB -VS
I
06286-057
Figure 57. Simplified Schematic
The AD8224 is a JFET input, monolithic instrumentation amplifier based on the classic three op amp topology (see Figure 57). Input Transistor J1 and Input Transistor J2 are biased at a fixed current so that any input signal forces the output voltages of A1 and A2 to change accordingly. The input signal creates a current through RG that flows in R1 and R2 such that the outputs of A1 and A2 provide the correct, gained signal. Topologically, J1, A1, R1 and J2, A2, R2 can be viewed as precision current feedback amplifiers with a gain bandwidth of 1.5 MHz. The common-mode voltage and amplified differential signal from A1 and A2 are applied to a difference amplifier that rejects the common-mode voltage but amplifies the differential signal. The difference amplifier employs 20 k laser trimmed resistors that result in an in-amp with gain error less than 0.04%. New trim techniques were developed to ensure that CMRR exceeds 86 dB (G = 1). Using JFET transistors, the AD8224 offers extremely high input impedance, extremely low bias currents of 10 pA maximum, low offset current of 0.6 pA maximum, and no input bias current noise. In addition, input offset is less than 125 V and drift is less than 5 V/C. Ease of use and robustness were considered. A common problem for instrumentation amplifiers is that at high gains, when the input is overdriven, an excessive milliampere input bias current can result and the output can undergo phase reversal. Overdriving the input at high gains refers to when the input signal is within the supply voltages but the amplifier cannot output the gained signal. For example, at a gain of 100, driving the amplifier with 10 V on 15 V constitutes overdriving the inputs since the amplifier cannot output 100 V.
The AD8224 has none of these problems; its input bias current is limited to less than 10 A and the output does not phase reverse under overdrive fault conditions. The AD8224 has extremely low load induced nonlinearity. All amplifiers that comprise the AD8224 have rail-to-rail output capability for enhanced dynamic range. The input of the AD8224 can amplify signals with wide common-mode voltages even slightly lower than the negative supply rail. The AD8224 operates over a wide supply voltage range. It can operate from either a single +4.5 V to +36 V supply or a dual 2.25 V to 18 V. The transfer function of the AD8224 is
G =1+ 49.4 k RG
Users can easily and accurately set the gain using a single, standard resistor. Since the input amplifiers employ a current feedback architecture, the AD8224 gain bandwidth product increases with gain, resulting in a system that does not experience as much bandwidth loss as voltage feedback architectures at higher gains.
GAIN SELECTION
Placing a resistor across the RG terminals sets the gain of the AD8224. This is calculated by referring to Table 11 or by using the following gain equation.
RG =
49.4 k G -1
Rev. PrB | Page 20 of 27
Preliminary Technical Data
Table 11. Gains Achieved Using 1% Resistors
1% Standard Table Value of RG () 49.9 k 12.4 k 5.49 k 2.61 k 1.00 k 499 249 100 49.9 Calculated Gain 1.990 4.984 9.998 19.93 50.40 100.0 199.4 495.0 991.0
AD8224
LAYOUT
The AD8224 is a high precision device. To ensure optimum performance at the PC board level, care must be taken in the design of the board layout. The AD8224 pinout is arranged in a logical manner to aid in this task.
Package Considerations
The AD8224 is available in a 16-lead, 4 mm x 4 mm LFCSP. Blindly copying the footprint from another 4 mm x 4 mm LFCSP part is not recommended; it may not have the same thermal pad size and leads. Refer to the Outline Dimensions section to verify that the PCB symbol has the correct dimensions. Space between the leads and thermal pad should be kept as wide as possible for the best bias current performance.
The AD8224 defaults to G = 1 when no gain resistor is used. The tolerance and gain drift of the RG resistor should be added to the AD8224's specifications to determine the total gain accuracy of the system. When the gain resistor is not used, gain error and gain drift are kept to a minimum.
Thermal Pad
The AD8224's 4 mm x 4 mm LFCSP comes with a thermal pad. This pad is connected internally to +VS. The pad can either be left unconnected or connected to the positive supply rail. To preserve maximum pin compatibility with future dual instrumentation amplifiers, leave the pad unconnected. This can be done by not soldering the paddle at all or by soldering the part to a landing that is a not connected to any other net. For high vibration applications, a landing is recommended. Because the AD8224 dissipates little power, heat dissipation is rarely an issue. If improved heat dissipation is desired (for example, when driving heavy loads), connect the thermal pad to the positive supply rail. For the best heat dissipation performance, the positive supply rail should be a plane in the board. See the section for thermal coefficients with and without the pad soldered.
REFERENCE TERMINAL
The output voltage of the AD8224 is developed with respect to the potential on the reference terminal. This is useful when the output signal needs to be offset to a precise midsupply level. For example, a voltage source can be tied to the REF1 or REF2 pin to level-shift the output so that the AD8224 can drive a singlesupply ADC. Pin REFx is protected with ESD diodes and should not exceed either +VS or -VS by more than 0.5 V. For best performance, source impedance to the REF terminal should be kept below 1 . As shown in Figure 57 the reference terminal, REF, is at one end of a 20 k resistor. Additional impedance at the REF terminal adds to this 20 k resistor and results in amplification of the signal connected to the positive input. The amplification from the additional RREF can be computed by
Common-Mode Rejection over Frequency
The AD8224 has a higher CMRR over frequency than typical in-amps, which gives it greater immunity to disturbances, such as line noise and its associated harmonics. A well-implemented layout is required to maintain this high performance. Input source impedances should be matched closely. Source resistance should be placed close to the inputs so that it interacts with as little parasitic capacitance as possible. Parasitics at the RGx pins can also affect CMRR over frequency. The PCB should be laid out so that the parasitic capacitances at each pin match. Traces from the gain setting resistor to the RGx pins should be kept short to minimize parasitic inductance.
2 (20 k + RREF )
40 k + RREF
Only the positive signal path is amplified; the negative path is unaffected. This uneven amplification degrades the amplifier's CMRR.
INCORRECT CORRECT CORRECT
AD8224
VREF VREF +
AD8224
VREF
AD8224
Reference
+
OP2177
-
AD8224
06286-058
-
Errors introduced at the reference terminal feed directly to the output. Take care to tie the REFx pins to the appropriate local ground.
Figure 58. Driving the Reference Pin
Rev. PrB | Page 21 of 27
AD8224
Power Supplies
A stable dc voltage should be used to power the instrumentation amplifier. Noise on the supply pins can adversely affect performance. The AD8224 has two positive supply pins (Pin 5 and Pin 16) and two negative supply pins (Pin 8 and Pin 13). While the part functions with only one pin from each supply pair connected, both pins should be connected for specified performance and optimum reliability. The AD8224 should be decoupled with 0.1 F bypass capacitors, one for each supply. The positive supply decoupling capacitor should be placed near Pin 16, and the negative supply decoupling capacitor should be placed near Pin 8. Each supply should also be decoupled with a 10 F tantalum capacitor. The tantalum capacitor can be placed further away from the AD8224 and can generally be shared by other precision integrated circuits. Figure 59 shows an example layout.
Preliminary Technical Data
INPUT BIAS CURRENT RETURN PATH
The input bias current of the AD8224 must have a return path to common. When the source, such as a transformer, cannot provide a return current path, one should be created, as shown in Figure 60.
INPUT PROTECTION
All terminals of the AD8224 are protected against ESD. ESD protection is guaranteed to 4 kV (human body model).In addition, the input structure allows for dc overload conditions a diode drop above the positive supply and a diode drop below the negative supply. Voltages beyond a diode drop of the supplies cause the ESD diodes to conduct and enable current to flow through the diode. Therefore, an external resistor should be used in series with each of the inputs to limit current for voltages above +Vs. In either scenario, the AD8224 safely handles a continuous 6 mA current at room temperature. For applications where the AD8224 encounters extreme overload voltages, as in cardiac defibrillators, external series resistors and low leakage diode clamps, such as BAV199L, FJH1100, or SP720, should be used.
INCORRECT
+VS
0.1F
CORRECT
+VS
16
15
14
13
AD8224
1 2 RG 3 4 10 9
C
AD8224
12 11 RG
-VS TRANSFORMER +VS C 1 fHIGH-PASS = 2RC REF C R R REF
AD8224
REF
-VS TRANSFORMER +VS
5
6
7
8
AD8224
C
AD8224
REF
0.1F
-VS
06286-059
CAPACITIVELY COUPLED
CAPACITIVELY COUPLED
Figure 60. Creating an IBIAS Path
Figure 59. Example Layout
SOLDER WASH
The solder process can leave flux and other contaminants on the board. When these contaminants are between the AD8224 leads and thermal pad, they can create leakage paths that are larger than the AD8224's bias currents. A thorough washing process removes these contaminants and restores the device's excellent bias current performance.
RF INTERFERENCE
RF rectification is often a problem in applications where there are large RF signals. The problem appears as a small dc offset voltage. The AD8224 by its nature has a 5 pF gate capacitance (CG) at its inputs. Matched series resistors form a natural low-pass filter that reduces rectification at high frequency (see Figure 61). The relationship between external, matched series resistors and the internal gate capacitance is expressed as follows:
Rev. PrB | Page 22 of 27
06286-060
-VS
Preliminary Technical Data
FilterFreq DIFF = FilterFreqCM = 1 R 2 CG 1 2RCG FilterFreqCM = 1 2R(CC + CG )
AD8224
Mismatched CC capacitors result in mismatched low-pass filters. The imbalance causes the AD8224 to treat what would have been a common-mode signal as a differential signal. To reduce the effect of mismatched external CC capacitors, select a value of CD greater than 10 times CC. This sets the differential filter frequency lower than the common-mode frequency.
+15V
+15V +
0.1F
10F
0.1F CC R 1nF +IN CD 10nF
10F
+
R
+IN CG -VS VOUT
4.02k
AD8224
REF -IN
VOUT
R 4.02k CC 1nF 0.1F -15V
AD8224
CG -VS REF
R -IN
10F
0.1F
10F
Figure 62. RFI Suppression
06286-061
+
-15V
COMMON-MODE INPUT VOLTAGE RANGE
The three op amp architecture of the AD8224 applies gain and then removes the common-mode voltage. Therefore, internal nodes in the AD8224 experience a combination of both the gained signal and the common-mode signal. This combined signal can be limited by the voltage supplies even when the individual input and output signals are not. Figure 26, Figure 27, Figure 28, and Figure 29 show the allowable common-mode input voltage ranges for various output voltages, supply voltages, and gains.
Figure 61. RFI Filtering Without External Capacitors
To eliminate high frequency common-mode signals while using smaller source resistors, a low-pass R-C network can be placed at the input of the instrumentation amplifier (see Figure 62). The filter limits the input signal bandwidth according to the following relationship: FilterFreq DIFF = 1 2R(2 CD + CC + CG )
Rev. PrB | Page 23 of 27
06286-062
+
AD8224 APPLICATIONS
DRIVING AN ANALOG-TO-DIGITAL CONVERTER
An instrumentation amplifier is often used in front of an analog-todigital converter to provide CMRR and additional conditioning such as a voltage level shift and gain (see Figure 63). In this example, a 2.7 nF capacitor and a 500 resistor create an anti aliasing filter for the AD7685. The 2.7 nF capacitor also serves to store and deliver necessary charge to the switched capacitor input of the ADC. The 500 series resistor reduces the burden of the 2.7 nF load from the amplifier. However, large source impedance in front of the ADC can degrade total harmonic distortion (THD). For applications where THD performance is critical, the series resistor needs to be small. At worst, a small series resistor can load the AD8224, potentially causing the output to overshoot or ring. In such cases, a buffer amplifier, such as the AD8615, should be used after the AD8224 to drive the ADC.
+5V +
Preliminary Technical Data
+IN RG -IN
+
AD8224
- -
20k
+OUT
AD8224
+
REF2
33pF +IN2
06286-064
-OUT
Figure 64. Differential Circuit Schematic
Setting the Common-Mode Voltage
The output common-mode voltage is set by the average of +IN2 and REF2. The transfer function is VCM_OUT = (V+OUT + V-OUT)/2 = (V+IN2 + VREF2)/2 +IN2 and REF2 have different properties that allow the reference voltage to be easily set for a wide variety of applications. +IN2 has high impedance but cannot swing to the supply rails of the part. REF2 must be driven with a low impedance, but can go 300 mV beyond the supply rails. A common application sets the common-mode output voltage to the midscale of a differential ADC. In this case, the ADC reference voltage is sent to the +IN2 terminal, and ground is connected to the REF2 terminal. This produces a commonmode output voltage of half the ADC reference voltage.
10F
0.1F
ADR435
+5V +IN 4.7F
50mV
1.07k -IN
AD8224
REF +2.5V
500 2.7nF
AD7685
Figure 63. Driving an ADC in a Low Frequency Application
06286-063
DIFFERENTIAL OUTPUT
The differential configuration of the AD8224 has the same excellent dc precision specifications as the single-ended output configuration and is recommended for applications in the frequency range of dc to 100 kHz. The circuit configuration, outlined in Table 7, refers to the configuration shown in Figure 64 only. The circuit includes an RC filter that maintains the stability of the loop. The transfer function for the differential output is:
VDIFF_OUT = V+OUT - V-OUT = (V+IN - V-IN) x G
2-Channel Differential Output Using a Dual Op Amp
Another differential output topology is shown in Figure 65. Instead of a second in-amp, 1/2 of a dual OP2177 op amp creates the inverted output. Because the OP2177 comes in an MSOP, this configuration allows the creation of a dual channel, precision differential output in-amp with little board area. Errors from the op amp are common to both outputs and are thus common mode. Errors from mismatched resistors also create a common-mode dc offset. Because these errors are common mode, they are likely to be rejected by the next device in the signal chain.
+IN
where:
G =1+ 49.4 k RG
AD8224
-IN REF 4.99k VREF
+OUT
4.99k
+ - OP2177
-OUT
Figure 65. Differential Output Using Op Amp
Rev. PrB | Page 24 of 27
06286-065
Preliminary Technical Data
+12V +
AD8224
10F
0.1F +5V 100pF NPO 1k 5% +OUT 1000pF (DIFF OUT) -OUT REF2 806 806 2.7nF 2.7nF 0.1F VDD
+IN
AD8224
IN+ IN-
AD7688
GND REF
-IN
1k 100pF NPO 5% +IN2
+5V REF 10F + 0.1F -12V 0.1F
+12V
10F X5R
VIN
VOUT 0.1F
+5V REF
ADR435
GND
Figure 66. Driving a Differential ADC
DRIVING A DIFFERENTIAL INPUT ADC
The AD8224 can be configured in differential output mode to drive a differential analog-to-digital converter. Figure 66 illustrates several of the concepts.
Reference
The ADR435 supplies a reference voltage to both the ADC and the AD8224. Because REF2 on the AD8224 is grounded, the common-mode output voltage is precisely half the reference voltage, exactly where it needs to be for the ADC.
First Antialiasing Filter
The 1 k resistor, 1000 pF capacitor, and 100 pF capacitors in front of the in-amp form a 76 kHz filter. This is the first of two antialiasing filters in the circuit and helps to reduce the noise of the system. The 100 pF capacitors protect against commonmode RFI signals. Note that they are 5% COG/NPO types. These capacitors match well over time and temperature, which keeps the system's CMRR high over frequency.
DRIVING CABLING
All cables have a certain capacitance per unit length, which varies widely with cable type. The capacitive load from the cable may cause peaking in the AD8224 output response. To reduce peaking, use a resistor between the AD8224 and the cable. Because cable capacitance and desired output response vary widely, this resistor is best determined empirically. A good starting point is 50 . The AD8224 operates at a low enough frequency that transmission line effects are rarely an issue; therefore, the resistor need not match the characteristic impedance of the cable.
Second Antialiasing Filter
An 806 resistor and 2.7 nF capacitor are located between each AD8224 output and ADC input. They create a 73 kHz low-pass filter for another stage of antialiasing protection. These four elements also isolate the ADC from loading the AD8224. The 806 resistor shields the AD8224 from the ADC's switched capacitor input which looks like a time varying load. The 2.7 nF capacitor provides charge to the switched capacitor front end of the ADC. If the application requires a lower frequency antialiasing filter, increase the value of the capacitor rather than the resistor. The 1 k resistors can also protect an ADC from overvoltages. Because the AD8224 runs on wider supply voltages than a typical ADC, there is a possibility of overdriving the ADC. This is not an issue with a PulSAR(R) converter, such as the AD7688. Its input can handle a 130 mA overdrive, which is much higher than the short-circuit limit of the AD8224. However, other converters have less robust inputs and may need the added protection.
AD8224
(DIFF OUT)
(SINGLE OUT)
AD8224
06286-066
Figure 67. Driving a Cable
Rev. PrB | Page 25 of 27
06286-067
AD8224 OUTLINE DIMENSIONS
4.00 BSC SQ 0.60 MAX
12 13
Preliminary Technical Data
0.50 0.40 0.30
PIN 1 INDICATOR
16
1
PIN 1 INDICATOR
3.75 BSC SQ 0.65 BSC TOP VIEW
9
EXPOSED PAD
4 8 5
2.65 2.50 SQ 2.35 0.25 MIN
1.95 BCS 0.80 MAX 0.65 TYP BOT TOM VIEW
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC.
Figure 68. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm x 4 mm Body, Very Thin Quad
(CP-16-13)
Dimensions are shown in millimeters
ORDERING GUIDE
Model AD8224ACPZ-R71 AD8224ACPZ-RL1 AD8224ACPZ-WP1 AD8224BCPZ-R71 AD8224BCPZ-RL1 AD8224BCPZ-WP1 AD8224-EVALZ
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Product Description 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ Evaluation Board
031006-A
12 MAX 1.00 0.85 0.80 SEATING 0.30 PLANE 0.23 0.18
0.05 MAX 0.02 NOM COPLANARITY 0.20 REF 0.08
Package Option CP-16-13 CP-16-13 CP-16-13 CP-16-13 CP-16-13 CP-16-13
Z = Pb-free part.
Rev. PrB | Page 26 of 27
Preliminary Technical Data NOTES
AD8224
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06286-0-12/06(PrB)
Rev. PrB | Page 27 of 27

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